The invention relates to improved layout design of high density integrated circuits, particularly circuits having a large number of circuit devices per cell such as six-transistor static random access memory devices and especially such circuits employing local interconnect pads.
In the field of VLSI integrated circuit design, a critical factor is, of course, density of cells and devices per unit area on the circuit. Complementary metal oxide semiconductor (CMOS) memory devices typically have one million or more memory cells per device with associated circuitry. Static random access memory (SRAM) devices are a popular type of memory device at this time due to their fast access time and ability to retain data for extended periods of time without refresh compared to dynamic random access memory devices. CMOS SRAM devices have six transistors per memory cell. Therefore, the individual cell size is even more critical in the design of these devices than in the design of devices having fewer elements per cell. A great deal of attention is therefore given to the circuit layout of the six-transistor SRAM.
A six-transistor SRAM cell, as is known in the art is shown in FIG. 1 which will now be briefly described. FIG. 1 illustrates a SRAM cell which, as known, can be incorporated into a CMOS or BiCMOS SRAM device. The cell is configured having cross coupled inverters consisting of p-channel transistor 6 and n-channel transistor 4 having their source-to-drain paths connected in series between V.sub.cc and ground and having their gates tied together and P-channel transistor 5 and n-channel transistor 3 connected in the same manner. Cross coupling is accomplished by the gates of transistors 4 and 6 being connected to the drains of transistors 3 and 5 and the gates of transistors 3 and 5 being connected to the drains of transistors 4 and 6. N-channel pass transistors 1 and 2 are connected at their gates to word line 7. Pass transistor is connected in its source-to-drain path between first bit line 9 and node 10. Pass transistor 2 is connected in its source-to-drain path between a second bit line 8 and node 11. The operation of the cell as is well known in the art forms no part of the invention and will not be further detailed here. For a detailed discussion of this operation, one is referred to U.S. patent application Ser. No. 156,520; assigned to the assignee of this application, the issue fee on this case was paid on May 1, 1989, assigned to the assignee of this invention (TI-13235).
Further refinement to the above described CMOS SRAM cell has been described in the literature and is the subject of copending U.S. patent application Ser. No. 837,478, assigned to the assignee of this application, having a common assignee with the instant application. This refinement relates to an improved cell layout of the six-transistor SRAM cell using local interconnect pads comprising TiN or similar materials to form interconnections bridging transistor source/drain regions to polysilicon (or other conductive material) conducting lines which form the gates of the transistors and form conducting lines between transistors in the cell. The use of local interconnect pads has increased the density of the cells in a device and reduced parasitic capacitance over cells using such interconnect means as metal jumpers. A typical cell configuration layout as used in SRAM fabrication using local interconnect pads as is known is illustrated in FIG. 2. The same reference numerals as used in FIG. 1 are used to indicate like elements. The cell configuration of FIG. 2 omits some elements such as via windows, metal lines, and other structural elements not necessary to illustrate the configuration of the prior art cell for the purposes of the explanation of the instant invention. Also, continuation of the cell elements as they interconnect and interface with the neighboring cells of the device are not shown to improve clarity. It will be understood, however, that the cell shown will typically be interconnected with up to one million or more cells of similar configuration in an SRAM device.
Shown in FIG. 2 are two p-moat regions 24 and 25 drawn in diagonal hatching. Overlying p-moat 24 is conducting line 31 which may be polysilicon. Transistor 6 is formed in the p-moat 24 having the overlying conducting line 31 as the gate. Conducting line 32 overlies p-moat 25. Likewise, transistor 5 is formed in p-moat 25 having conducting line 32 forming its gate where it overlies the p-moat. Conducting line 32 may also be polysilicon. Between conducting lines 31 and 32 and respective moats 24 and 25 is a gate dielectric (not shown) as is well known in the art. Local interconnect pads 30 and 26 shown in bold outline overlie and connect a source/drain region of transistor 6 with conducting line 32 and a source/drain region of transistor 5 with conducting line 31, respectively. Similarly, transistors 4 and 3 are formed in n-moat 23 and n-moat 21, respectively, having conducting line 31 as the gate of transistor 4 and conducting line 32 as the gate of transistor 3. Again, a gate dielectric (not shown) separates the gates from the moat region. Local interconnect pad 27 overlies and connects a source/drain region of transistor 4 with conducting line 32 and local interconnect pad 28 overlies and connects a source/drain region of transistor 3 and conducting line 31. Pass transistor 1 is formed from the same n-moat region 21 as transistor 3 and having as its gate overlying word line 7 which may be polycrystalline silicon. Conducting line 31 and 32 and word line 7 are shown in random dot pattern for clarity. N-moats 21, 22, and 23 are shown in horizontal and vertical crosshatching. Different crosshatching patterns are used for the purpose of clarity and are not intended to designate specific materials or conductivity as in convention. Finally, pass transistor 2 is formed in n-moat 22 with overlying word line 7 as its gate. Local interconnect pad 29 overlies and connects a source/drain region of transistor 2 and conducting line 32. N-moat 22 and n-moat 21 connect by means not shown to a first and second bit line (not shown).
As shown in FIG. 2, the resulting six-transistor SRAM cell occupies a generally rectangular area having a major axis which is considerably longer than the minor axis thereof. Although FIG. 2 is not intended to be drawn to scale, it approximates the shape of the cell as it is actually fabricated in an SRAM device. Design rules and other design considerations of the cell in practice have resulted in a cell which occupies a rectangle having relatively long and narrow dimensions.
Some of the design rules which must be considered when designing a six-transistor SRAM cell utilizing local interconnect pads, and, in fact in the design of other type memory cells and other devices will be explained with reference to FIG. 3a. A moat 34 underlies a conducting line 31. These two elements are generally separated by a dielectric (not shown). A transistor may be formed from these elements. Conducting line 32 is located outside of moat 34. Local interconnect pad overlies and connects moat region 34 and conducting line 32. As is well known, design rules must be formulated and applied to any integrated circuit design configuration or process. These rules specify minimum (or maximum) distances for reliability and operation of the device. The rules are dependent upon many factors such as the variability in dimensions of the structures fabricated and the variability in alignment of one structural material to another. Both variabilities depend in turn on fabrication techniques applied and tolerances of the equipment used in fabrication. Illustrated in FIG. 3a are five minimum design rules which together dictate the minimum width that the configuration shown may be fabricated. Distance "a" is the minimum line width for a polysilicon conducting line for a given device and fabrication process. A minimum distance "a" may be, for example, 0.8 .mu.m. Note that the distances specified herein for design rules are exemplary only and would vary for different configurations and design processes. Distance "b" is the distance required between two conducting lines. A typical minimum distance "b" may be 1.0 .mu.m. Distance "c" represents the minimum allowed distance between a local interconnect pad and an unrelated conducting line. This distance may be, for example, 0.7 .mu.m. Distance "d" is the distance that the local interconnect pad overlaps the moat region. A typical minimum design rule for distance "d" is 0.8 .mu.m, e.g. Distance "e" is the distance that the local interconnect pad overlaps the conducting line. A typical design rule minimum for distance "e" may be 0.6 .mu.m. As can be seen then, the minimum width for this configuration from one conducting line to the other, including the width of both lines, must be at least a+c+d+e+(a-e). For the exemplary design rule distances given above this would result in a minimum distance of 3.1 .mu.m. Additionally, it can be seen that the alignment of the local interconnect pad over the conducting line is critical to achieve minimum distance "e" while not extending over the conducting line to thereby increase the width.